CodeV-Series

module top_module(
  input clk,
  input [7:0] d,
  input areset,
  output reg [7:0] q);
  always @(posedge clk, posedge areset) begin
    if (areset == 1) begin
      q <= 0;
    end
    else begin
      q <= d;
    end
  end
endmodule
                    

module top_module(
  input clk,
  input load,
  input [1:0] ena,
  input [99:0] data,
  output reg [99:0] q);
	always @(posedge clk) begin
		if(load)
			q <= data;
		else if(ena == 2'h1)
			q <= {q[0], q[99:1]};
		else if(ena == 2'h2)
			q <= {q[98:0], q[99]};
	end
endmodule
                    

module top_module(
  input ring, 
  input vibrate_mode,
  output ringer,
  output motor
);
  assign ringer = ring & (~vibrate_mode);
  assign motor = ring & vibrate_mode;
endmodule
                    

module top_module (
  input clk,
  input aresetn,
  input x,
  output reg z
);
  reg [1:0] state, next_state;
  parameter A = 0, B = 1, C = 2;
  always @(*) begin
    case (state)
      A: next_state = x ? B : A;
      B: next_state = x ? B : C;
      C: next_state = x ? B : A;
    endcase
  end
  always @(posedge clk, negedge aresetn) begin
    if (~aresetn)
      state <= A;
    else
      state <= next_state;
  end
  always @(*) begin
    z = (state == C) & x;
  end
endmodule

                    

import chisel3._
import chisel3.util._

class TopModule extends Module {
    val io = IO(new Bundle {
    val reset = Input(Bool())
    val q = Output(UInt(4.W))  
    })
  val counter = RegInit(1.U(4.W))
  when(counter === 10.U) {
    counter := 1.U
  } .otherwise {
    counter := counter + 1.U
  }
  io.q := counter
  when(io.reset) {
    counter := 1.U
  }
}
                    

class Mux4 extends Module {
val io = IO(new Bundle {
  val in0 = Input(UInt(1.W))
  val in1 = Input(UInt(1.W))
  val in2 = Input(UInt(1.W))
  val in3 = Input(UInt(1.W))
  val sel = Input(UInt(2.W))
  val out = Output(UInt(1.W))
})
  val m0 = Module(new Mux2())
  m0.io.sel := io.sel(0)
  m0.io.in0 := io.in0
  m0.io.in1 := io.in1
  val m1 = Module(new Mux2())
  m1.io.sel := io.sel(0)
  m1.io.in0 := io.in2
  m1.io.in1 := io.in3
  val m2 = Module(new Mux2())
  m2.io.sel := io.sel(1)
  m2.io.in0 := m0.io.out
  m2.io.in1 := m1.io.out
  io.out := m2.io.out
}
                    

module TopModule (
  input clk,
  input reset,
  input [7:0] in,
  output reg [23:0] out_bytes,
  output reg done
);

    reg [1:0] count;
    reg [7:0] byte1, byte2;

    always @(posedge clk) begin
        if (reset) begin
            count <= 2'b00;
            done <= 1'b0;
            byte1 <= 8'h00;
            byte2 <= 8'h00;
            out_bytes <= 24'h0;
        end else begin
            done <= 1'b0; // Default done to 0
            
            case (count)
                // State 0: Waiting for first byte with in[3] == 1
                2'b00: begin
                    if (in[3]) begin
                        byte1 <= in;
                        count <= 2'b01; // Move to state 1
                    end
                end
                // State 1: Captured first byte, waiting for second
                2'b01: begin
                    byte2 <= in;
                    count <= 2'b10; // Move to state 2
                end
                // State 2: All three bytes received; output and done
                2'b10: begin
                    out_bytes <= {byte1, byte2, in};
                    done <= 1'b1;
                    count <= 2'b00; // Reset for next message
                end
                default: count <= 2'b00;
            endcase
        end
    end

endmodule
                  

module TopModule (input [4:1] x, output f);
  assign f = (x[3] & ~x[1]) | (~x[3] & x[4] & x[1] & x[2]);
endmodule
                  

module FullAdder (
  input a,
  input b,
  input cin,
  output sum,
  output cout
);
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (a & cin) | (b & cin);
endmodule

module TopModule (
    input [3:0] x,
    input [3:0] y,
    output [4:0] sum
);
    wire c0, c1, c2;
    
    FullAdder FA0 (
        .a(x[0]),
        .b(y[0]),
        .cin(1'b0),
        .sum(sum[0]),
        .cout(c0)
    );
    
    FullAdder FA1 (
        .a(x[1]),
        .b(y[1]),
        .cin(c0),
        .sum(sum[1]),
        .cout(c1)
    );
    
    FullAdder FA2 (
        .a(x[2]),
        .b(y[2]),
        .cin(c1),
        .sum(sum[2]),
        .cout(c2)
    );
    
    FullAdder FA3 (
        .a(x[3]),
        .b(y[3]),
        .cin(c2),
        .sum(sum[3]),
        .cout(sum[4])
    );
endmodule
                  

module div_16bit(
  input [15:0] A,
  input [7:0] B,
  output [15:0] result,
  output [15:0] odd
);

    reg [15:0] a_reg;
    reg [7:0] b_reg;
    reg [15:0] quotient;
    reg [15:0] remainder;
    integer i;

    // First combinational block to capture inputs
    always @* begin
        a_reg = A;
        b_reg = B;
    end

    // Second combinational block for division logic
    always @* begin
        remainder = 16'd0;
        quotient = 16'd0;
        for (i = 15; i >= 0; i = i - 1) begin
            remainder = (remainder << 1) | a_reg[i];
            if (remainder >= {8'd0, b_reg}) begin
                remainder = remainder - {8'd0, b_reg};
                quotient[i] = 1;
            end else begin
                quotient[i] = 0;
            end
        end
    end

    assign result = quotient;
    assign odd = remainder;

endmodule